Hitachi SH7750 Hardware Manual page 10

Sh7750 series superh risc engine

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13.1.4 Register Configuration 318

13.1.5 Overview of Areas

13.2.1 Bus Control Register

13.2.2 Bus Control Register

13.2.3 Bus Control Register

3 (BCR3) (SH7750R Only)

13.2.4 Bus Control Register

13.2.5 Wait Control Register

13.2.6 Wait Control Register

13.2.7 Wait Control Register

Rev. 6.0, 07/02, page x of I

Table 13.2 BSC Registers

Table 13.3 External Memory

Space Divisions

Table 13.3 External Memory

Memory Bus Width

Bit 31, Bit 30, Bit 29

Bit 15, Bit 14

Bits 13 to 11

Bits 10 to 8

Bits 12 to 1—Reserved

Bits 31 to 29, Bits 25 to 23,

Bits 19 to 17, Bits 15 to 13,

Bits 11 to 9, Bits 8 to 6,

Bits 5 to 3, and Bits 2 to 0

Bus control register 3

and 4 added to table,

and Note added

added to Area 0, 5,

6 Settable Bus Widths,

and Note 7 added

Description amended

Table amended, and

Notes amended and

Description added

Bit 18 amended and

Description added

Description and notes

Description amended

Table amended and

Description amended

Description added

Description added

Note amended

Description added and

Bits 19 and 7 changed,

and Note added

Description added

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Hitachi SH7750 Hardware Manual page 10

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