Hitachi SH7750 Hardware Manual page 394

Sh7750 series superh risc engine

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Bits 31 to 29—Area 6 Wait Control (A6W2—A6W0): These bits specify the number of wait

states to be inserted for area 6. For details on MPX interface setting, see table 13.6, MPX Interface

is Selected (Areas 0 to 6).

Bit 31: A6W2

Bit 30: A6W1

Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to

be inserted from the second data access onward in a burst transfer with the burst ROM interface

Bit 28: A6B2

Bit 27: A6B1

Rev. 6.0, 07/02, page 344 of 986

Bit 29: A6W0

Inserted Wait States

15 (Initial value)

Wait States Inserted

from Second Data

Bit 26: A6B0

Access Onward

7 (Initial value)

Burst Cycle (Excluding First Cycle)

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