Bus Control Register 3 (Bcr3) (Sh7750R Only) - Hitachi SH7750 Hardware Manual

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Bus Control Register 3 (BCR3) (SH7750R Only)

Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of

either the MPX interface or the SRAM interface and specifies the burst length when the

synchronous DRAM interface is used.

BCR3 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in

standby mode. No external memory space other than area 0 should be accessed before register

initialization has been completed.

Initial value:

Initial value:

Bit 15    A1MPX/A4MPX Enable (MEMMODE): Determines whether or not the selection of

either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by

Bit 15: MEMMODE

Bits 14 and 13    MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These

bits specify the types of memory connected to areas 1 and 4. These settings are validated by

Bit 14: A1MPX

Bit 13: A4MPX

MPX or SRAM interface is selected by MEMMPX

MPX or SRAM interface is selected by A1MPX and A4MPX

SRAM/byte control SRAM interface is selected for area 1

MPX interface is selected for area 1

SRAM/byte control SRAM interface is selected for area 4

MPX interface is selected for area 4

(Initial value)

Rev. 6.0, 07/02, page 337 of 986

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