Toshiba GR-200 Series Instruction Manual page 271
Multi functional protection ied
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Also See for GR-200 Series:
- Instruction manual (1770 pages) ,
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ARCCO-OCEN
ARCCO-EFEN
From flop-flops behind
ARC IN-PROG OR
ARC shot logics
From Initiation logic
ARC_START
ARC NOT-IN-PROG
From Initiation logic
From final trip logic
ARC SHOT OVER
From shot-counter logic
MULTI-ARC INIT
From shot-counter logic
SHOT_3RD
From shot-counter logic
SHOT_4TH
SHOT_5TH
From shot-counter logic
From shot-counter logic
SHOT_6TH
†Note: To reset the operation of the ARC function, delay timers 'TCORST*' are provided
for 'ARC SHOT2' to 'ARC SHOT5', respectively. The values of the 'TCORST' are
defined in the rules of Table 2.22-2.
Table 2.22-2 Delay timers in the shot number coordination logic
Delay timer
TCORST2
TCORST3
TCORST4
TCORST5
Miscellaneous feature
2.22.7
Scheme switch [SHOTNUM-Test] is provided for testing the ARC function. For example, if the
user wishes to test autoreclosing to reach the 'ARC SHOT4' stage, regardless of the setting of
[ARC-NUM], set S4 for the [SHOTNUM-Test]. Note Off must be selected for this setting when
the ARC function is in normal service.
t
0
A
&
CO-OC
t
0
B
&
t
0
C
&
1CYCLE
On
t
0
CO-EF
&
1CYCLE
On
Figure 2.22-18 Shot number coordination logic
Retarding time for resetting
Setting [TD_MS2]+setting [TARCDSUC]
Setting [TD_MS3]+setting [TARCDSUC]
Setting [TD_MS4]+setting [TARCDSUC]
Setting [TD_MS5]+setting [TARCDSUC]
0 t
Sensing a
&
different
0 t
duration for the
pick-up and
0 t
drop-off of fault
current
1CYCLE
performed by the
CO-OC and
CO-EF elements
to determine
operation of the
0 t
coordination
function.
1CYCLE
1
≥1
- 252 -
6F2T0200 (0.15)
To Shot counter logic and
8100001B7C
1
0 t
1CYCLE
3CYCLES
S
R
&
≥1
t
0
1.5 CYCLE
t
0
&
TCORST2†
t
0
&
≥1
TCORST3†
t
0
&
TCORST4†
t
0
&
TCORST5†
GRE200 (1,2)
Success check logic
ARC COORD
To Initiation logic
1
ARC RS
0.1s
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