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DSP56367 Overview
DSP56300 Core Functional Blocks
1.4.7
JTAG TAP AND ONCE MODULE
The DSP56300 core provides a dedicated user-accessible TAP fully compatible with the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with
testing high-density circuit boards led to developing this standard under the sponsorship of the
Test Technology Committee of IEEE and JTAG. The DSP56300 core implementation
supports circuit-board test strategies based on this standard.
The test logic includes a TAP consisting of four dedicated signals, a 16-state controller, and
three test data registers. A boundary scan register links all device signals into a single shift
register. The test logic, implemented utilizing static logic design, is independent of the device
system logic. More information on the JTAG port is provided in DSP56300 Family Manual,
JTAG Port.
The OnCE module provides a nonintrusive means of interacting with the DSP56300 core and
its peripherals so a user can examine registers, memory, or on-chip peripherals. This
facilitates hardware and software development on the DSP56300 core processor. OnCE
module functions are provided through the JTAG TAP signals. More information on the
OnCE module is provided in DSP56300 Family Manual, On-Chip Emulation Module.
1.4.8
ON-CHIP MEMORY
The memory space of the DSP56300 core is partitioned into program memory space,
X data memory space, and Y data memory space. The data memory space is divided into X
and Y data memory in order to work with the two Address ALUs and to feed two operands
simultaneously to the Data ALU. Memory space includes internal RAM and ROM and can be
expanded off-chip under software control.
There is an instruction cache, made using program RAM. The patch mode (which uses
instruction cache space) is used to patch program ROM. The memory switch mode is used to
increase the size of program RAM as needed (switch from X data RAM and/or Y data RAM).
There are on-chip ROMs for program memory (40K x 24-bit), bootstrap memory (192 words
x 24-bit), X ROM (32K x 24-bit), and Y ROM(8K x 24-bit).
More information on the internal memory is provided in Section 5 Internal I/O Memory
Map on page 5-14.
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DSP56367
MOTOROLA
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