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11.3.8
ESAI_1 RECEIVE SHIFT REGISTERS
The receive shift registers receive the incoming data from the serial receive data pins. Data is
shifted in by the selected (internal/external) bit clock when the associated frame sync I/O is
asserted. Data is assumed to be received MSB first if RSHFD=0 and LSB first if RSHFD=1.
Data is transferred to the ESAI_1 receive data registers after 8, 12, 16, 20, 24, or 32 serial
clock cycles were counted, depending on the slot length control bits in the RCR_1 register.
11.3.9
ESAI_1 RECEIVE DATA REGISTERS
The Receive Data Registers RX3_1, RX2_1, RX1_1, and RX0_1 are 24-bit read-only
registers that accept data from the receive shift registers when they become full. The data
occupies the most significant portion of the receive data registers, according to the ALC
control bit setting. The unused bits (least significant portion, and 8 most significant bits when
ALC=1) read as zeros. The DSP is interrupted whenever RXx_1 becomes full if the associated
interrupt is enabled.
11.3.10 ESAI_1 TRANSMIT SHIFT REGISTERS
The Transmit Shift Registers contain the data being transmitted. Data is shifted out to the
serial transmit data pins by the selected (internal/external) bit clock when the associated frame
sync I/O is asserted. The number of bits shifted out before the shift registers are considered
empty and may be written to again can be 8, 12, 16, 20, 24 or 32 bits (determined by the slot
length control bits in the TCR_1 register). Data is shifted out of these registers MSB first if
TSHFD=0 and LSB first if TSHFD=1.
11.3.11 ESAI_1 TRANSMIT DATA REGISTERS
The Transmit Data registers TX5_1, TX4_1, TX3_1, TX2_1, TX1_1, and TX0_1 are 24-bit
write-only registers. Data to be transmitted is written into these registers and is automatically
transferred to the transmit shift registers. The data written (8, 12, 16, 20 or 24 bits) should
occupy the most significant portion of the TXx_1 according to the ALC control bit setting.
The unused bits (least significant portion, and the 8 most significant bits when ALC=1) of the
TXx_1 are don't care bits. The DSP is interrupted whenever the TXx_1 becomes empty if the
transmit data register empty interrupt has been enabled.
MOTOROLA
Enhanced Serial Audio Interface 1 (ESAI_1)
DSP56367
ESAI_1 Programming Model
11-13
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