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In network mode, this ratio may be interpreted as the number of words per frame minus one.
The divide ratio may range from 2 to 32 (RDC[4:0]=00001 to 11111) for network mode. A
divide ratio of one (RDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from
1 to 32 (RDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of one
(RDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync
(RFSL=1) must be used in this
The ESAI frame sync generator functional diagram is shown in Figure 10-4.
10.3.3.4
RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17
The RFP3–RFP0 bits control the divide ratio of the receiver high frequency clock to the
receiver serial bit clock when the source of the receiver high frequency clock and the bit clock
is the internal DSP clock. When the HCKR input is being driven from an external high
frequency clock, the RFP3-RFP0 bits specify an additional division ration in the clock divider
chain. See Table 10-6 for the specification of the divide ratio. The ESAI high frequency
generator functional diagram is shown in Figure 10-3.
Table 10-6 Receiver High Frequency Clock Divider
10.3.3.5
RCCR Receiver Clock Polarity (RCKP) - Bit 18
The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync
are clocked out and latched in. If RCKP is cleared the data and the frame sync are clocked out
on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge
of the receive bit clock. If RCKP is set the falling edge of the receive clock is used to clock the
data and frame sync out and the rising edge of the receive clock is used to latch the frame sync
in.
10.3.3.6
RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19
The Receiver Frame Sync Polarity (RFSP) determines the polarity of the receive frame sync
signal. When RFSP is cleared the frame sync signal polarity is positive (i.e the frame start is
indicated by a high level on the frame sync pin). When RFSP is set the frame sync signal
polarity is negative (i.e the frame start is indicated by a low level on the frame sync pin).
MOTOROLA
case.
RFP3-RFP0
$0
$1
$2
$3
...
$F
DSP56367
Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
Divide Ratio
1
2
3
4
...
16
10-27
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