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8.4
HDI08 BLOCK DIAGRAM
Figure 8-1 shows the HDI08 registers. The top row of registers (HCR, HSR, HDDR, HDR,
HBAR, HPCR, HOTX, HORX) can be accessed the DSP core. The bottom row of registers
(ISR, ICR, CVR, IVR, RXH:RXM:RXL and TXH:TXM:TXL) can be accessed by the host
processor.
24
24
HCR
HSR
HDDR
ICR
ISR
CVR
8
8
ICR
Interface Control Register
CVR
Command Vector Register
ISR
Interface Status Register
IVR
Interrupt Vector Register
RXH/RXM/RXL
Receive Register High/Middle/Low
TXH/TXM/TXL
Transmit Register High/Middle/Low
MOTOROLA
Core DMA Data Bus
DSP Peripheral Data Bus
24
24
24
HDR
HBAR
8
Address
Comparator
5
3
IVR
Latch
8
8
8
HOST Bus
Figure 8-1 HDI08 Block Diagram
DSP56367
Host Interface (HDI08)
HDI08 Block Diagram
24
24
HPCR
HOT
24
RXH
RXM
RXL
3
8
8
8
HCR
Host Control Register
HSR
Host Status Register
HPCR
Host Port Control Register
HBAR
Host Base Address register
HOTX
Host Transmit register
HORX
Host Receive register
HDDR
Host Data Direction Register
HDR
Host Data Register
24
24
24
HOR
24
TXH
TXM
RXL
8
8
8
8-5
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