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HBUSY is cleared otherwise. HBUSY is cleared by hardware reset, software reset, SHI
individual reset, and during the stop state.
9.6
CHARACTERISTICS OF THE I
2
The I
C serial bus consists of two bidirectional lines, one for data signals (SDA) and one for
clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply
voltage via a pull-up resistor.
2
Note:
In the I
C bus specifications, the standard mode (100 kHz clock rate) and a fast
mode (400 kHz clock rate) are defined. The SHI can operate in either mode.
9.6.1
OVERVIEW
2
The I
C bus protocol must conform to the following rules:
•
Data transfer may be initiated only when the bus is not busy.
•
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line when the clock line is high are interpreted as control signals
(see Figure 9-7).
SDA
SCL
2
Accordingly, the I
C bus protocol defines the following events:
•
Bus not busy—Both data and clock lines remain high.
•
Start data transfer—The start event is defined as a change in the state of the data
line, from high to low, while the clock is high (see Figure 9-8).
MOTOROLA
2
C BUS
Data Line
Change
Stable:
of Data
Data Valid
Allowed
2
Figure 9-7 I
C Bit Transfer
DSP56367
Serial Host Interface
Characteristics Of The I
2
C Bus
AA0422
9-19
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