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•
Program address bus (PAB) for carrying program memory addresses throughout the
core
•
X memory address bus (XAB) for carrying X memory addresses throughout the core
•
Y memory address bus (YAB) for carrying Y memory addresses throughout the core
All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1-1.
1.4.5
DIRECT MEMORY ACCESS (DMA)
The DMA block has the following features:
•
Six DMA channels supporting internal and external accesses
•
One-, two-, and three-dimensional transfers (including circular buffering)
•
End-of-block-transfer interrupts
•
Triggering from interrupt lines and all peripherals
1.4.6
PLL-BASED CLOCK OSCILLATOR
The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which
performs clock input division, frequency multiplication, and skew elimination; and the clock
generator (CLKGEN), which performs low-power division and clock pulse generation.
PLL-based clocking:
•
Allows change of low-power divide factor (DF) without loss of lock
•
Provides output clock with skew elimination
•
Provides a wide range of frequency multiplications (1 to 4096), predivider factors (1 to
16), and a power-saving clock divider (2
The PLL allows the processor to operate at a high internal clock frequency using a low
frequency clock input. This feature offers two immediate benefits:
•
A lower frequency clock input reduces the overall electromagnetic interference
generated by a system.
•
The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.
MOTOROLA
DSP56300 Core Functional Blocks
i
: i = 0 to 7) to reduce clock noise
DSP56367
DSP56367 Overview
1-9
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