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Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
10.3.6
ESAI STATUS REGISTER (SAISR)
The Status Register (SAISR) is a read-only status register used by the DSP to read the status
and serial input flags of the ESAI. See Figure 10-12. The status bits are described in the
following paragraphs.
11
X:$FFFFB3
23
10.3.6.1
SAISR Serial Input Flag 0 (IF0) - Bit 0
The IF0 bit is enabled only when the SCKR pin is defined as ESAI in the Port Control
Register, SYN=1 and RCKD=0, indicating that SCKR is an input flag and the synchronous
mode is selected. Data present on the SCKR pin is latched during reception of the first
received data bit after frame sync is detected. The IF0 bit is updated with this data when the
receiver shift registers are transferred into the receiver data registers. IF0 reads as a zero when
it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF0.
10.3.6.2
SAISR Serial Input Flag 1 (IF1) - Bit 1
The IF1 bit is enabled only when the FSR pin is defined as ESAI in the Port Control Register,
SYN =1, RFSD=0 and TEBE=0, indicating that FSR is an input flag and the synchronous
mode is selected. Data present on the FSR pin is latched during reception of the first received
data bit after frame sync is detected. The IF1 bit is updated with this data when the receiver
shift registers are transferred into the receiver data registers. IF1 reads as a zero when it is not
enabled. Hardware, software, ESAI individual, and STOP reset clear IF1.
10.3.6.3
SAISR Serial Input Flag 2 (IF2) - Bit 2
The IF2 bit is enabled only when the HCKR pin is defined as ESAI in the Port Control
Register, SYN=1 and RHCKD=0, indicating that HCKR is an input flag and the synchronous
mode is selected. Data present on the HCKR pin is latched during reception of the first
received data bit after frame sync is detected. The IF2 bit is updated with this data when the
receive shift registers are transferred into the receiver data registers. IF2 reads as a zero when
it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF2.
10-38
10
9
8
7
RODF REDF
RDF
ROE
22
21
20
19
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-12 SAISR Register
DSP56367
6
5
4
3
RFS
18
17
16
15
TODE TEDE
TDE
2
1
0
IF2
IF1
IF0
14
13
12
TUE
TFS
MOTOROLA
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