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12.3
DAX FUNCTIONAL OVERVIEW
The DAX consists of the following:
•
Audio data register (XADR)
•
Two audio data buffers (XADBUFA and XADBUFB)
•
Non-audio data register (XNADR)
•
Non-audio data buffer (XNADBUF)
•
Audio and non-audio data shift register (XADSR)
•
Control register (XCTR)
•
Status register (XSTR)
•
Parity generator (PRTYG)
•
Preamble generator
•
Biphase encoder
•
Clock multiplexer
•
Control state machine
XADR, XADBUFA, XADBUFB and XADSR creates a FIFO-like data path. Channel A is
written to XADR and moves to XADBUFA. Then channel B is written to XADR, and when
XADBUFB empties XADR moves into it. XADBUFA moves to the shift register XADSR
when XADSR has shifted out its last bit. After channel A audio and non-audio data has been
shifted out, XADBUFB moves into XADSR, and channel B audio and non audio shift begins.
The frame non-audio data (stored in XNADR) is transferred to the XADSR (for channel A)
and to the XNADBUF registers (for channel B) at the beginning of a frame transmission. This
is called an "upload." The DAX audio data register empty (XADE) flag is set when XADR
and XADBUFA are empty, and, if the audio data register empty interrupt is enabled
(XDIE=1), an interrupt request is sent to the DSP core. The interrupt handling routine then
sends the non-audio data bits to XNADR and the next frame of audio data to XADR (two
subframes).
At the beginning of a frame transmission, one of the 8-bit channel A preambles (Z-preamble
for the first subframe in a block, or X-preamble otherwise) is generated in the preamble
generator, and then shifted out to the ADO pin in the first eight time slots. The preamble is
generated in biphase mark format. The twenty-four audio and three non-audio data bits in the
XADSR are shifted out to the biphase encoder, which shifts them out through the ADO pin in
the biphase mark format in the next 54 time slots. The parity generator calculates an even
parity over the 27 bits of audio and non-audio data, and then outputs the result through the
MOTOROLA
DSP56367
12-3
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