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Note:
In this mode, internal logic preserves the TIO0 value and direction for an
additional 2.5 internal clock cycles after the DSP56367 hardware RESET signal is
asserted. This ensures that a valid RESET signal is generated when the TIO0
signal is used to reset the DSP56367.
13.4.4.2
Watchdog Toggle (Mode 10)
Bit Settings
TC3
TC2
TC1
1
0
1
In this mode, the timer generates an interrupt at a preset rate. Timer 0 also toggles the output
on TIO0.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is
loaded into the TPCR. The counter is loaded with the TLR value on the first timer clock
received from either the DSP56367 internal clock divided by two (CLK/2) or the prescaler
clock output. Each subsequent timer clock increments the counter. The TIO0 signal is set to
the value of the INV bit.
When the counter equals the value in the TCPR, the TCF bit in the TCSR is set, and a
compare interrupt is generated if the TCIE bit is also set. If the TRM bit is set, the counter is
loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is
cleared, the counter continues to be incremented on each subsequent timer clock
When counter overflow has occurred, the polarity of the TIO0 output pin is inverted, the TOF
bit in the TCSR is set, and an overflow interrupt is generated if the TOIE bit is also set. The
TIO0 polarity is determined by the INV bit.
The counter is reloaded whenever the TLR is written with a new value while the TE bit is set.
This process is repeated until the timer is disabled by clearing the TE bit. The counter contents
can be read at any time by reading the TCR register.
Note:
In this mode, internal logic preserves the TIO0 value and direction for an
additional 2.5 internal clock cycles after the DSP56367 hardware RESET signal is
asserted. This ensures that a valid RESET signal is generated when the TIO0
signal is used to reset the DSP56367.
MOTOROLA
TC0
Mode
NAME
0
10
Toggle
DSP56367
Timer/ Event Counter
Timer Modes of Operation
Mode Characteristics
Kind
TIO0
Watchdog
Output
Clock
Internal
13-23
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