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Philips Semiconductors
ARM-based Microcontroller
Table 56: Pin description for LPC2292/2294
Pin
LQFP144
Name
Pin #
102
95
86
82
70
60
52
144
140
126
113
43
98,105,106,10
8,109,114-
P2.0
118,120,124,1
to
25,127,129-
P2.31
134,136,137,1,
10-13,16-20
98
105
106
108
109
Pin Configuration
Type
P1.20
TRACESYNCTrace Synchronization. Standard I/O port with internal pull-up.
O
P1.21
PIPESTAT0 Pipeline Status, bit 0. Standard I/O port with internal pull-up.
O
P1.22
PIPESTAT1 Pipeline Status, bit 1. Standard I/O port with internal pull-up.
O
P1.23
PIPESTAT2 Pipeline Status, bit 2. Standard I/O port with internal pull-up.
O
P1.24
TRACECLK Trace Clock. Standard I/O port with internal pull-up.
O
P1.25
EXTIN0
I
P1.26
RTCK
I/O
P1.27
TDO
O
P1.28
TDI
I
P1.29
TCK
I
P1.30
TMS
I
P1.31
TRST
I
Port 2: Port 2 is a 32-bit bi-directional I/O port with individual direction controls for each bit.
I/O
The operation of port 2 pins depends upon the pin function selected via the Pin Connect
Block.
P2.0
D0
I/O
P2.1
D1
I/O
P2.2
D2
I/O
P2.3
D3
I/O
P2.4
D4
I/O
Description
LOW on this pin while RESET is LOW enables pins P1.25:16 to
operate as a Trace port after reset.
External Trigger Input. Standard I/O with internal pull-up.
Returned Test Clock output. Extra signal added to the JTAG
port. Assists debugger synchronization when processor
frequency varies. Bi-directional pin with internal pullup. LOW on
this pin while RESET is LOW enables pins P1.31:26 to operate
as a Debug port after reset.
Test Data out for JTAG interface.
Test Data in for JTAG interface.
Test Clock for JTAG interface.
Test Mode Select for JTAG interface.
Test Reset for JTAG interface.
External memory data line 0.
External memory data line 1.
External memory data line 2.
External memory data line 3.
External memory data line 4.
95
Preliminary User Manual
LPC2119/2129/2292/2294
January 08, 2004
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