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Philips Semiconductors
ARM-based Microcontroller
Error Warning Limit Register (CANEWL - 0xE00x x018)
This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read at any time, but can only be written if
the RM bit in CANmod is 1.
Table 130: CAN Error Warning Limit Register (CANEWL - 0xE00x x018)
CANEWL Name Function
During CAN operation, this value is compared to both the Tx and Rx Error Counters.
7:0
EWL
If either of these counter matches this value, the Error Status (ES) bit in CANSR is
set.
Status Register (CANSR - 0xE00x x01C)
This register contains three status bytes, in which the bits not related to tranmission are identical to the corresponding bits in the
Global Status Register, while those relating to transmission reflect the status of each of the 3 Tx Buffers.
Table 131: CAN Status Register (CANSR - 0xE00x x01C)
CANSR
Name
Function
0, 8, 16
RBS
These bits are identical to the RSB bit in the GSR.
1, 9, 17
DOS
These bits are identical to the DOS bit in the GSR.
1: software may write a message into the CANTFI, CANTID, CANTDA, and
TBS1,
CANTDB registers for this Tx Buffer.
2, 10, 18
TBS2,
0: software should not write to any of the CANTFI, CANTID, CANTDA, and
TBS3
CANTDB registers for this Tx Buffer.
TCS1,
1: The previously requested transmission for this Tx Buffer has been successfully
3, 11, 19
TCS2,
completed.
TCS3
0: The previously requested transmission for this Tx Buffer is not complete.
4, 12, 20
RS
These bits are identical to the RS bit in the GSR.
TS1,
5, 13, 21
TS2,
1: The CAN Controller is transmitting a message from this Tx Buffer.
TS3
6, 14, 22
ES
These bits are identical to the ES bit in the GSR.
7, 15, 23
BS
These bits are identical to the BS bit in the GSR.
CAN Controllers and Acceptance Filter
LPC2119/2129/2292/2294
165
Preliminary User Manual
Reset Value RM Set
96
=0x60
X
10
Reset Value RM Set
0
0
0
0
1
X
1
0
0
0
0
0
0
0
0
0
January 08, 2004
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