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Philips Semiconductors
ARM-based Microcontroller
CENTRALIZED CAN REGISTERS
Three read-only registers group the bits in the Status registers of the CAN controllers for common accessibility. If devices with
more or fewer CAN controllers are defined, the number of bits used in the active bytes will change correspondingly. Each defined
byte of the following registers contains one particular status bit from each of the CAN controllers, in its LS bits.
Central Transmit Status Register (CANTxSR - 0xE004 0000)
Table 142: CAN Central Transmit Status Register (CANTxSR - 0xE004 0000)
CANTxSR
Name
5:0
TS6:1
13:8
TBS6:1
21:16
TCS6:1
Central Receive Status Register (CANRxSR - 0xE004 0004)
Table 143: CAN Central Receive Status Register (CANRxSR - 0xE004 0004)
CANRxSR
Name
5:0
RS6:1
13:8
RBS6:1
21:16
DOS6:1
Central Miscellaneous Status Register (CANMSR - 0xE004 0008)
Table 144: CAN Central Miscellaneous Status Register (CANMSR - 0xE004 0008)
CANMSR
Name
5:0
ES6:1
13:8
BS6:1
GLOBAL ACCEPTANCE FILTER
This block provides lookup for received Identifiers (called Acceptance Filtering in CAN terminology) for all the CAN Controllers.
It includes a 512 x 32 (2K byte) RAM in which software maintains one to five tables of Identifiers. This RAM can contain up to
1024 Standard Identifiers or 512 Extended Identifiers, or a mixture of both types.
If Standard (11-bit) Identifiers are used in the application, at least one of 3 tables in Acceptance Filter RAM must not be empty.
If the optional "fullCAN mode" is enabled, the first table contains Standard identifiers for which reception is to be handled in this
mode. The next table contains individual Standard Identifiers and the third contains ranges of Standard Identifiers, for which
messages are to be received via the CAN Controllers. The tables of fullCAN and individual Standard Identifiers must be
arranged in ascending numerical order, one per halfword, two per word. Since each CAN bus has its own address map, each
entry also contains the number of the CAN Controller (001-110) to which it applies.
CAN Controllers and Acceptance Filter
Function
1: the CAN controller is sending a message (same as TS in the CANGSR)
1: all 3 Tx Buffers are available to the CPU (same as TBS in CANGSR)
1: all requested transmissions have been completed successfully (same as TCS in
CANGSR)
Function
1: the CAN controller is receiving a message (same as RS in CANGSR)
1: a received message is available in the CAN controller (same as RBS in CANGSR)
1: a message was lost because the preceding message to this CAN controller was not
read out quickly enough (same as DOS in CANGSR)
Function
1: one or both of the Tx and Rx Error Counters has reached the limit set in the EWL
register (same as ES in CANGSR)
1: the CAN controller is currently involved in bus activities (same as BS in CANGSR)
LPC2119/2129/2292/2294
171
Preliminary User Manual
Reset Value
0
1
1
Reset Value
0
0
0
Reset Value
0
0
January 08, 2004
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