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Philips Semiconductors
ARM-based Microcontroller
PIN DESCRIPTION
Table 222: EmbeddedICE Pin Description
Pin Name
Type
TMS
Input
TCK
Input
TDI
Input
TDO
Output
nTRST
Input
DBGSEL
Input
RTCK
Output
RESET STATE OF MULTIPLEXED PINS
On the LPC2119/2129/2292/2294, the pins above are multiplexed with P1.31-26. To have them come up as a Debug port,
connect a weak bias resistor (4.7 kΩ) between VSS and the P1.26/RTCK pin. To have them come up as GPIO pins, do not
connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-
impedance state, during Reset.
EmbeddedICE Logic
Test Mode Select. The TMS pin selects the next state in the TAP state machine.
Test Clock. This allows shifting of the data in, on the TMS and TDI pins. It is a positive edge-
triggered clock with the TMS and TCK signals that define the internal state of the device.
Test Data In. This is the serial data input for the shift register.
Test Data Output. This is the serial data output from the shift register. Data is shifted out of the
device on the negative edge of the TCK signal
Test Reset. The nTRST pin can be used to reset the test logic within the EmbeddedICE logic.
Debug Select. When low at Reset, the P0.17 - P0.21 pins are configured for alternate functions
via the Pin Connect Block. When high at Reset, debug mode is entered.
For functionality provided by DBGSEL see "" section of this chapter.
Returned Test Clock. Extra signal added to the JTAG port. Required for designs based on
ARM7TDMI-S processor core. Multi-ICE (Development system from ARM) uses this signal to
maintain synchronization with targets having slow or widely varying clock frequency. For details
refer to "Multi-ICE System Design considerations Application Note 72 (ARM DAI 0072A)".
LPC2119/2129/2292/2294
Description
251
Preliminary User Manual
January 08, 2004
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