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Philips Semiconductors
ARM-based Microcontroller
Interrupt Request, Masking, and Selection
SoftIntClear
[31:0]
SoftInt
[31:0]
VICINT
SOURCE
[31:0]
RawInterrupt
[31:0]
Vector Interrupt 0
Source Enable
VectorCntl[5:0]
Vector Interrupt 1
Vector Interrupt 15
Vectored Interrupt Controller (VIC)
IntEnableClear
[31:0]
FIQStatus
[31:0]
IntEnable
[31:0]
IRQStatus
[31:0]
IntSelect
[31:0]
Priority 0
VectIRQ0
VectorAddr
VectAddr0[31:0]
[31:0]
Priority 1
VectIRQ1
VectAddr1[31:0]
Priority 2
Priority 14
VectIRQ15
VectAddr15[31:0]
Priority 15
Figure 18: Block Diagram of the Vectored Interrupt Controller
nVICFIQIN
Non-vectored FIQ Interrupt Logic
FIQStatus
[31:0]
Non-vectored IRQ Interrupt Logic
IRQStatus
[31:0]
Interrupt Priority Logic
Hardware
Priority
Logic
Default
VectorAddr
[31:0]
nVICIRQIN
VICVECTADDRIN[31:0]
84
Preliminary User Manual
LPC2119/2129/2292/2294
nVICFIQ
IRQ
NonVectIRQ
IRQ
nVICIRQ
Address Select for
Highest Priority
Interrupt
VICVECT
VectorAddr
ADDROUT
[31:0]
January 08, 2004
[31:0]
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