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Philips Semiconductors
ARM-based Microcontroller
BLOCK DIAGRAM
The block diagram of the Watchdog is shown below in the Figure 45.
FEED ERROR
FEED
SEQUENCE
FEED OK
WDFEED
pclk
WDTV
REGISTER
1. Counter is enabled only when the WDEN bit is set
and a valid feed sequence is done.
2. WDEN and WDRESET are sticky bits. Once set
they can't be cleared until the Watchdog underflows
or an external reset occurs.
Watchdog
WDTC
32-BIT DOWN
/ 4
COUNTER
CURRENT WD
TIMER COUNT
SHADOW BIT
WDMOD
WDEN
REGISTER
Figure 45: Watchdog Block Diagram
226
LPC2119/2129/2292/2294
UNDER
FLOW
ENABLE
1
COUNT
2
WDTOF
WDINT
Preliminary User Manual
2
WDRESET
RESET
INTERRUPT
January 08, 2004
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