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the differential voltage, and the latter suppresses any overvoltage in the differential circuit.
Scheme Logic
Figure 2.3.2 to Figure 2.3.5 show the scheme logic of inverse time or definite time selective earth
fault protection and definite time earth fault protection on model 420, 421 and -422.
In Figures 2.3.2 and 2.3.3, the definite time protection is selected by setting [MSE1] and [MSE2] to
"D". The element SEF1 is enabled for sensitive earth fault protection and stage 1 trip signal
SEF1-S1 TRIP is given through the delayed pick-up timer TSE1. The element SEF2 is enabled and
trip signal SEF2 TRIP is given through the delayed pick-up timer TSE2.
The inverse time protection is selected by setting [MSE1] and [MSE2] to either "IEC", "IEEE",
"US" or "C" according to the inverse time characteristic to employ. The element SEF1 is enabled
and stage 1 trip signal SEF1-S1 TRIP is given. The element SEF2 is enabled and trip signal SEF2
TRIP is given.
The SEF1 protection provide stage 2 trip signal SEF1-S2 through a delayed pick-up timer TSE1
S2.
When the standby earth fault protection is applied by introducing earth current from the
transformer low voltage neutral circuit, stage 1 trip signals are used to trip the transformer low
voltage circuit breaker. If SEF1-D or SEF1-I continues operating after stage 1 has operated, the
stage 2 trip signal can be used to trip the transformer high voltage circuit breaker(s).
The signal SEF1 HS is used for blocked overcurrent protection and blocked busbar protection
(refer to Section 2.9)
SEF protection can be disabled by the scheme switch [SE1EN] and [SE2EN] or binary input signal
SEF1 BLOCK and SEF2 BLOCK. Stage 2 trip of standby earth fault protection can be disabled by
the scheme switch [SE1S2].
ICD is the inrush current detector ICD, which detects second harmonic inrush current during
transformer energisation, and can block the SEF*-D element by sheme switch [SE*-2F]. See
Section 2.9
In Figures 2.3.4 and 2.3.5, SEF3 and SEF4 protections are programmable for instantaneous or
definite time delayed operations with setting of delayed pick-up timers TSE3 and TSE4 and give
trip signals SEF3 TRIP and SEF4 ALARM.
F
Power
Transformer
Varistor
GRE110
Stabilising
SEF input
Resistor
Figure 2.3.1 High Impedance REF
24
6 F 2 T 0 1 7 2
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