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6 F 2 T 0 1 7 2
IDMT characteristics are not fully utilised. In this case, definite time overcurrent protection is
applied. The operating time can be constant irrespective of the magnitude of the fault current.
The definite time overcurrent protection consists of instantaneous overcurrent measuring elements
OC1 and EF1 and delayed pick-up timers started by the elements, and provides selective protection
with graded setting of the delayed pick-up timers. Thus, the constant time coordination with the
downstream section can be maintained as shown in Figure 2.1.4 As is clear in the figure, the nearer
to the power source a section is, the greater the delay in the tripping time of the section. This is
undesirable particularly where there are many sections in the series.
Operate time
T
C
T
C
A
B
C
Figure 2.1.4 Definite Time Overcurrent Protection
2.1.3
Scheme Logic
Figure 2.1.5 and Figure 2.1.6 show the scheme logic of the phase fault and earth fault overcurrent
protection with selective definite time or inverse time characteristic.
The definite time protection is selected by setting [MOC1] and [MEF1] to "D". Definite time
overcurrent elements OC1-D and EF1-D are enabled for phase fault and earth fault protection
respectively, and trip signal OC1 TRIP and EF1 TRIP are given through the delayed pick-up timer
TOC1 and TEF1.
The inverse time protection is selected by setting [MOC1] and [MEF1] to either "IEC", "IEEE" or
"US" according to the IDMT characteristic to employ. Inverse time overcurrent elements OC1-I
and EF1-I are enabled for phase fault and earth fault protection respectively, and trip signal OC1
TRIP and EF1 TRIP are given.
ICD is the inrush current detector ICD, which detects second harmonic inrush current during
transformer energisation etc. , and can block the OC1-D element by the scheme switch [OC1-2F]
respectively. See Section 2.9.
The signals OC1 HS and EF1 HS are used for blocked overcurrent protection and blocked busbar
protection (refer to Section 2.12).
These protections can be disabled by the scheme switches [OC1EN] and [EF1EN] or binary input
signals OC1 BLOCK and EF1 BLOCK.
OC2 and EF2 are provided with the same logic of OC1 and EF1.
12
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