Toshiba TLCS-900/H1 Series Manual page 262

Original cmos 32-bit microcontroller

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Stage change condition of control write (no data stage) transfer type

SETUP DATA0 ACK

INT_ ENDPOINT0

REQUEST FLAG

DATASET register

bmRequestType register

bRequest register

wValue register

wINdex register

wLength register

Figure 3.10.8 The Control Flow in UDC (Control Write Transfer Type not Dataphase)

Receive SETUP token from host

Start setup stage in UDC.

Receive data in request normally and judge. And assert INT_SETUP

interrupt externally.

Change data stage in the UDC.

Receive IN token from host

CPU receives a request from the request register every INT_SETUP

Judge request and access Setup Received register to inform the UDC

that INT_SETUP interrupt has been recognized.

The CPU processes receiving data by device request.

When the CPU finishes transaction, it writes "0" to EP0 bit of EOP

Change status stage in the UDC.

Return data packet of 0 data to IN token and change state to IDLE in

Assert INT_STATUS interrupt externally when ACK for 0 data

packet is received.

These change condition is Figure 3.10.8.

Setup Received register

EOP register

Tmp92ch21fg Jtmp92ch21