Toshiba TLCS-900/H1 Series Manual page 113
Original cmos 32-bit microcontroller
Hide thumbs
Also See for TLCS-900/H1 Series:
Advertisement
(2) Connection memory specification
Setting the <BnOM1:0> bit of the control register (BnCSH) specifies the memory
type that is connected with the block address areas. The interface signal is outputted
according to the set memory as follows.
<BnOM1: 0> Bit (BnCSH Register)
<BnOM1>
0
0
1
1
Note 1: SDRAM should be set to block either 1 or 2.
Note 2: Set "00" for NAND flash, RAM built-in LCDD.
(3) Data bus width specification
The data bus width is set for every block address area. The bus size is set by setting
the control register (BnCSH)<BnBUS1:0> as follows.
<BnBUS1:0> bit (BnCSH Register)
BnBUS 1
0
0
1
1
Note: SDRAM should be set to either "01" (16-bit bus) or "10" (32-bit bus).
This method of changing the data bus width depending on the accessing address is
called "dynamic bus sizing". The part of the data bus to which the data is output
depends on the data size, baus width and start address.
Note: Since there is a possibility of abnormal writing/reading of the data if two memories
with different bus width are put in consecutive addresses, do not execute an
access to both memories with one command.
<BnOM0>
Function
0
SRAM/ROM (Default)
1
(Reserved)
0
(Reserved)
1
SDRAM
BnBUS 0
Function
0
8-bit bus mode (Default)
1
16-bit bus mode
0
32-bit bus mode
1
Don't use this setting
92CH21-111
TMP92CH21
2009-06-19
Advertisement
