Toshiba TLCS-900/H1 Series Manual page 167
Original cmos 32-bit microcontroller
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(3) Serial clock generation circuit
This circuit generates the basic clock for transmitting and receiving data.
•
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC> = 0, the basic clock is
generated by dividing the output of the baud rate generator by 2, as described
previously.
In SCLK input mode with the setting SC0CR<IOC> = 1, the rising edge or falling
edge will be detected according to the setting of the SC0CR<SCLKS> register to
generate the basic clock.
•
In UART mode
The SC0MOD0<SC1:0> setting determines whether the baud rate generator
clock, the internal clock f
clock (SCLK0) is used to generate the basic clock SIOCLK.
(4) Receiving counter
The receiving counter is a 4-bit binary counter used in UART mode, which counts up
the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each
data bit is sampled three times, on the 7th, 8th and 9th clock cycles.
The value of the data bit is determined from these three samples using the majority
rule.
For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th
clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is
taken to be 0.
(5) Receiving control
•
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC> = 0, the RXD0 signal is
sampled on the rising edge or falling of the shift clock, which is output on the
SCLK0 pin, according to the SC0CR<SCLKS> setting.
In SCLK input mode with the setting SC0CR<IOC> = 1, the RXD0 signal is
sampled on the rising or falling edge of the SCLK0 input, according to the
SC0CR<SCLKS> setting.
•
In UART mode
The receiving control block has a circuit which detects a start bit using the
majority rule. Received bits are sampled three times; when two or more out of
three samples are 0, the bit is recognized as the start bit and the receiving
operation commences.
The values of the data bits that are received are also determined using the
majority rule.
, the match detect signal from TMRA0 or the external
IO
92CH21-165
TMP92CH21
2009-06-19
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