Toshiba TLCS-900/H1 Series Manual page 249
Original cmos 32-bit microcontroller
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(a-1) Transmission bulk mode
Below is the transaction format for bulk transfer during transmitting.
•
Token: IN
•
Data: DATA0/DATA1, NAK, STALL
•
Handshake: ACK
Control flow
Below is the control-flow when the UDC receives an IN token.
1.
The token packet is received and the address endpoint number error is confirmed,
and it checks whether the relevant endpoint transfer mode corresponds with the
IN token. If it does not correspond, the state returns to IDLE.
2.
Condition of EPx_STATUS register is confirmed.
•
INVALID condition: State returns to IDLE.
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STALL condition: Stall handshake is returned and state returns to IDLE.
FIFO condition is confirmed, if data number of 1 packet is not prepared, NAK
handshake is returned, and state returns to IDLE.
If data number of 1 packet is prepared to FIFO, it shifts to 3.
3.
Data packet is generated.
Data packet generated by using toggle bit register in UDC.
Next, data is transferred from FIFO of internal UDC to SIE, and data packet is
generated. At this point, the transferred data number is confirmed. And if there is
more than the maximum payload size of each endpoint, bit stuff error is generated,
transfer is finished, and STATUS becomes STALL.
4.
CRC bit (counted transfer data of FIFO from first to last) is attached to last.
5.
When ACK handshake from host is received,
•
Clear FIFO.
•
Clear DATASET register.
•
Renew toggle bit, and prepare for next.
•
Set STATUS to READY.
UDC finishes normally. FIFO can receive the next data.
If a time out occurs without receiving ACK from host,
•
Set STATUS to TX_ERR.
•
Return FIFO address pointer.
Execute above setting. And wait next retry keeping FIFO data.
This flow is shown in Figure 3.10.3.
92CH21-247
TMP92CH21
2009-06-19
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