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Single boot mode
RAMP(ch 0)
CRC
APB
CG
IO
IB(INTIF)
IMN(INTIF)
IA(INTIF)
RLM
LVD
ADC
OPAMP
T32A
UART
PORT
TRM
OFD
A-PMD
A-ENC32
A-VE+
Flash(SFR)
APB: Advanced Peripheral Bus, AO: 8bit-Bus for Backup domain, IO: 32bit-Bus for Main domain
Cortex M4(with FPU)
S-Bus
S0
S1
M0
M1
M2
M3
(Note)
M4
M5
M6
M7
M8
M9
S0
S1
Clock
Synchronous
circuit
DMAC
NBDIF
SS0
SS1
SM0
SM1
SM2
SM3
AO
SM4
APB
SM5
SM6
APB
SM7
SM8
IO
SS0
SS1
Note:Access to DataFlash is only for DMAC
Figure 2.4 Single boot mode
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Clock Control and Operation Mode
D-Bus
I-Bus
S2
S3
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
S2
S3
Clock
Synchronous
circuit
SS2
SM0
SM1
SM2
SM3
SM4
SM5
SM6
SM7
SM8
SS2
TXZ+ Family
TMPM4M Group(1)
Code Flash
Data Flash
Boot ROM
RAM0
RAM1
RAM2
CAN
TSPI
I2C
APB
EI2C
DNF
APB
TRGSEL
SIWDT
NBDIF
RAMP(ch 1)
DMAC(SFR)
2022-06-24
Rev. 1.1
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