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1.2.6. System clock
An internal high speed oscillation clock or external high speed oscillation clock (connected oscillator or clock
input) can be used as a source of system clock.
The system clock consists of "High speed system clock (fsysh)(maximum 160MHz )" for high speed operation
and "Middle speed system clock (fsysm)(maximum 80MHz)" which is generated by dividing High speed system
clock. Middle speed system clock is used by peripheral function to save power dissipation without degrading CPU
performance. The clock domains of the peripheral function can be checked in Table 1.4.
High speed system clock can be generated by dividing fc using [CGSYSCR]<GEAR[2:0]> (Clock gear). And
Middle speed system clock is generated by dividing the high speed system clock using [CGSYSCR]
<MCKSEL[1:0]>. Although a setting can be changed during operation, after register writing before the clock
actually changes, a time interval shown in Table 1.5 is required. The completion of the clock change should be
checked by [CGSYSCR]<GEARST[2:0]> <MCKSELGST[1:0]>.
Clock domain
High speed system clock
Middle speed system clock
System clock
Note1: The clock gear and the system clock should not be changed while the peripheral function such as the
timer/counter is operating.
Note2: An access between High speed system clock domain and Middle speed system clock domain cannot be
done when the system clock is changing.
The table below shows the example of operation frequency by the clock gear ratio (1/1 to 1/16) to the frequency fc
set up with oscillation frequency, a PLL multiplication value, etc.
External
Built-in
External
Clock
oscillation
Oscillation
input
IHOSC1
(MHz)
(MHz)
(MHz)
6
6
8
8
10
10
12
12
Table 1.4 Clock domains of CPU and peripherals
CPU, Code FLASH, Data FLASH, Boot ROM, RAM0/1, CG,
INTIF(IB, IMN), CRC, RAMP(ch0)
DMAC, NBDIF, SIWDT, UART, CAN, TSPI, I
OPAMP, Port, A-PMD, A-ENC32, A-VE+, INTIF(IA), DNF, LVD,
TRM, FLASH(SFR), OFD, RAMP(ch1) , RLM, TRGSEL, RAM2
Table 1.5 Time interval for changing System clock
High speed (fsysh)
fsys
16 fc cycles at maximum
fsys/2
fsys/4
Table 1.6 Example of operation frequency
PLL
Maximum
Multiplication
Frequency
value
(fc)(MHz)
(after dividing)
-
26.66
159.94
-
20
10
16
-
13
Block
Middle speed (fsysm)
16 fc cycles at maximum
-
32 fc cycles at maximum
-
64 fc cycles at maximum
Operation frequency (MHz)
by the clock gear ratio
PLL=ON
1/1
1/2
1/4
159.94
79.97
39.99
160
160
80
40
160
160
80
40
156
156
78
39
18 / 64
TMPM4M Group(1)
Clock Control and Operation Mode
2
2
C, EI
C, T32A, ADC,
Operation frequency (MHz)
by the clock gear ratio
1/8
1/16
1/1
1/2
19.99
10.00
6
20
10
8
20
10
10
19.5
9.75
12
TXZ+ Family
PLL=OFF
1/4
1/8
1/16
3
1.5
-
-
4
2
1
-
5
2.5
1.25
-
6
3
1.5
-
2022-06-24
Rev. 1.1
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