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Note4: To wait stabilizing oscillation of an internal high speed oscillator 1 (IHOSC1) , use a warming-up timer
and confirm [CGWUPHCR]<WUEF> instead of <IHOSC1F>.
[CGSYSCR] (System clock control register)
Bit
Bit Symbol
31:30 MCKSELPST[1:0]
29:28
-
27:24
PRCKST[3:0]
23:22 MCKSELGST[1:0]
21:19
-
18:16
GEARST[2:0]
15:12
-
11:8
PRCK[3:0]
7:6
MCKSEL[1:0]
5:3
-
2:0
GEAR[2:0]
After reset
Type
Middle speed prescaler clock (ΦT0m) selection status
00: <PRCK[3:0]> setting value (no division)
00
R
01: <PRCK[3:0]> setting value is divided by 2
10,11: <PRCK[3:0]> setting value is divided by 4
0
R
Read as "0".
High speed prescaler clock (ΦT0h) selection status
0000: fc
0000
R
0001: fc/2
0010: fc/4
0011: fc/8
Middle speed system clock (fsysm) selection status
00: <GEAR[2:0]> setting value (no division)
00
R
01: <GEAR[2:0]> setting value is divided by 2
10,11: <GEAR[2:0]> setting value is divided by 4
0
R
Read as "0".
High speed system clock (fsysh) gear selection status
000: fc
000
R
001: fc/2
010: fc/4
011: fc/8
0
R
Read as "0".
High speed prescaler clock (ΦT0h) selection
0000: fc
0001: fc/2
0000
R/W
0010: fc/4
0011: fc/8
Selects a prescaler clock for the peripheral functions.
Middle speed system clock (fsysm) and Middle speed prescaler
clock (ΦT0m) selection
00: <GEAR[2:0]>,<PRCK[3:0]> setting values (no division)
00
R/W
01: <GEAR[2:0]>,<PRCK[3:0]> setting values are divided by 2.
10,11: <GEAR[2:0]>,<PRCK[3:0]> setting values are divided by 4.
Maximum operating frequency of middle speed system clock is
80MHz.
0
R
Read as "0".
High speed system clock (fsysh) gear selection
000: fc
000
R/W
001: fc/2
010: fc/4
011: fc/8
32 / 64
Clock Control and Operation Mode
Function
0100: fc/16
1000: fc/256
0101: fc/32
1001: fc/512
0110: fc/64
1010 to 1111: Reserved
0111: fc/128
100: fc/16
101 to 111: Reserved
0100: fc/16
1000: fc/256
0101: fc/32
1001: fc/512
0110: fc/64
1010 to 1111: Reserved
0111: fc/128
100: fc/16
101 to 111: Reserved
TXZ+ Family
TMPM4M Group(1)
2022-06-24
Rev. 1.1
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