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1.2. Clock control
1.2.1. Clock type
This section shows a list of clocks:
EHCLKIN: The high speed clock input from the external
f
: A clock generated in the internal oscillation circuit or input from the X1 and X2 pins
OSC
f
: A clock multiplied with PLL
PLL
fc
: A clock selected by [CGPLL0SEL]<PLL0SEL> (High speed clock)
fsysh
: A high speed system clock selected by [CGSYSCR]<GEAR[2:0]>
fsysm
: A middle speed system clock selected by [CGSYSCR]<GEAR[2:0]><MCKSEL[1:0]>
ΦT0h
: A high speed clock selected by [CGSYSCR]<PRCK[3:0]> (High speed prescaler clock)
ΦT0m
: A middle speed clock selected by [CGSYSCR]<PRCK[3:0]> <MCKSEL[1:0]> (Middle speed
prescaler clock)
f
: A clock generated with the internal high speed oscillator 1
IHOSC1
f
: A clock generated with the internal high speed oscillator 2
IHOSC2
ADCLK : A conversion clock for ADC
TRCLKIN: A clock for tracing facilities of a debugging circuit (Trace or SWV)
Note: The high speed system clock and the middle speed system clock are collectively called System clock
(fsys). And the high speed prescaler clock and the middle speed prescaler clock are collectively called
Prescaler clock (ΦT0).
1.2.2. The initial value by a reset action
A clock setup is initialized to the following states by a reset action.
External high speed oscillator
Internal high speed oscillator 1
Internal high speed oscillator 2
PLL (multiplying circuit)
Gear clock
: Stop
: Oscillation
: Stop
: Stop
: fc (no frequency dividing)
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TMPM4M Group(1)
Clock Control and Operation Mode
TXZ+ Family
2022-06-24
Rev. 1.1
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