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[CGSTBYCR] (Standby control register)
Bit
Bit Symbol
31:2
-
1:0
STBY[1:0]
[CGPLL0SEL] (PLL selection register for fsys)
Bit
Bit Symbol
31:8
PLL0SET[23:0]
7:3
-
2
PLL0ST
1
PLL0SEL
0
PLL0ON
After reset
Type
0
R
Read as "0".
Selects a low power consumption mode.
00: IDLE
00
R/W
01: STOP1
10: Reserved
11: Reserved
After reset
Type
PLL0 multiplication setup
0x000000
R/W
About a multiplication setup, refer to the "1.2.5.2. The formula and
the example of a setting of a PLL multiplication value".
0
R
Read as "0".
Indicates PLL for fsys selection status.
0
R
0: f
OSC
1: f
PLL
Selects Clock selection for fsys
0
R/W
0: f
OSC
1: f
PLL
Selects PLL operation for fsys
0
R/W
0: Stop
1: Oscillation
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TMPM4M Group(1)
Clock Control and Operation Mode
Function
Function
TXZ+ Family
2022-06-24
Rev. 1.1
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