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1.2.3. Clock System diagram
The figure below shows a clock system diagram.
[CGWUPHCR]<WUON>
[CGWUPHCR]<WUPT[15:4]>
Warming-up timer
[CGWUPHCR]
<WUCLK>
[CGOSCCR]<IHOSC1EN>
Internal
High-speed
oscillator1
[CGOSCCR]<EOSCEN>
External
X2
High speed
X1
oscillator
EHCLKIN
[CGOSCCR]<IHOSC2EN>
TARGET
EHOSC
Internal
High-speed
REF
oscillator2
SIWDT
fc
1/2 1/4 1/8 1/16
High speed
PLL0
fosc
[CGOSCCR]
<OSCSEL>
fosc
OFD
[CGSYSCR]
<MCKSEL[1:0]>
1/2 1/4
[CGSYSCR]
<GEAR[2:0]>
1/2 1/4
[CGSYSCR]
1/32
1/64
1/128
1/256
1/512
<PRCK[3:0]>
Figure 1.1 Clock system diagram
Clock Control and Operation Mode
[CGSPCLKEN]
<ADCKEN[3:0]>
fc
[CGFCEN]
<FCIPEN[31:0]>
f
PLL
fc
[CGPLL0SEL]
<PLL0SEL>
[CGSPCLKEN]
<TRCKEN>
fsysm
fsysh
ΦT0m
[CGFSYSMENA]
<IPENA[31:0]>
[CGFSYSMENB]
<IPENB[31:0]>
ΦT0h
[CGFSYSENA]
<IPENA[31:0]>
12 / 64
TXZ+ Family
TMPM4M Group(1)
ADCLK
ADC
Peripheral function using fc
DNF, OFD(Target clock)
fc
(To fsys and ΦT0 generation)
SysTick
1/64
CPU
TRCK
TRCLKIN
1/4
fsysh
Peripheral function using fsysm
fsysm
RAM2, LVD,
INTIF(IA),
PORT, TSPI, UART, I2C, EI2C,
CAN, T32A, ADC, OPAMP,
A-ENC32, A-PMD, A-VE+,
RAMP(ch1), OFD, TRM, TRGSEL,
DMAC, NBDIF, SIWDT, Flash(SFR)
Peripheral function using fsysh
fsysh
Code Flash, Data Flash, Boot ROM,
RAM0/1, INTIF(IB, IMN)
CRC, RAMP(ch0)
Peripheral function using ΦT0m
TSPI, UART, T32A
Peripheral function using ΦT0h
N/A
DEBUG
RLM
ΦT0m
ΦT0h
2022-06-24
Rev. 1.1
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