Table of Contents
Advertisement
The directions for a warming-up timer
The directions for a warming-up function are explained.
(1) Selection of a clock
In a high speed oscillation, the clock classification (an internal oscillation/external oscillation) counted
with a warming-up timer is selected by [CGWUPHCR]<WUCLK>.
(2) Calculation of a warming-up timer setting value
The warming-up time can set any value to the timer for a high speed oscillation. Please compute and set
up from the formula.
(3) The start of warming-up, and a termination Confirmation
When software (command) performs the start of warming-up, starting warming-up count is carried out
by setting [CGWUPHCR]<WUON> to "1". Termination is confirmed with [CGWUPHCR]<WUEF>
that becomes from "1" to "0". "1" shows that it is warming-up and "0" shows termination. After a
counting end, a timer is reset and returns to an initial state.
It is not forced to terminate, although "0" is written to [CGWUPHCR]<WUON> during timer operation.
Writing "0" is disregarded.
Note: Since it is operating with the oscillating clock, a warming-up timer includes an error, when Oscillation
frequency has fluctuation. Therefore, it serves an approximate time.
1.2.5. Clock multiplying circuit (PLL) for fsys
The clock multiplying circuit outputs the f
the frequency (6 MHz to 12 MHz) of the output clock f
So, it is possible to make input frequency to an oscillator low and to make an internal clock high speed by this
circuit.
A PLL setup after reset release
The PLL is disabled after reset release.
In order to use the PLL, set [CGPLL0SEL]<PLL0SET[23:0]> to a multiplication value while [CGPLL0SEL]
<PLL0ON> is "0". Then wait until approximately 100 μs has elapsed as a PLL initial stabilization time, and set
<PLL0ON> to "1" to start PLL operation. After that, to use f
approximately 400 μs has elapsed as a lock up time. Then set [CGPLL0SEL]<PLL0SEL> to "1".
Note that a time is required until PLL operation becomes stable using the warming-up function, etc.
clock (maximum 160MHz) multiplied by the optimum condition for
PLL
of the high speed oscillator.
OSC
clock which is multiplied f
PLL
14 / 64
TMPM4M Group(1)
Clock Control and Operation Mode
, wait until
OSC
TXZ+ Family
2022-06-24
Rev. 1.1
Advertisement
Table of Contents
