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specifications. A standard interface between the DSP56300 core and the on-chip memory
and peripherals supports a wide variety of memory and peripheral configurations.
The DSP56309 targets telecommunications applications, such as multi-line
voice/data/fax processing, video conferencing, audio applications, control, and general
digital signal processing.
1.5
DSP56309 CORE DESCRIPTION
The DSP56300 Family Manual fully describes core features; this manual describes
pinout, memory, and peripheral features.
1.5.1
General Features
¥ 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0 -
3.6 V
¥ Object-code compatible with the DSP56000 core
¥ Highly parallel instruction set
1.5.2
Hardware Debugging Support
¥ On-Chip Emulation (OnCEÔ) module
¥ Joint Test Action Group (JTAG) test access port (TAP)
¥ Address trace mode reflects internal program RAM accesses at the external port
1.5.3
Reduced Power Dissipation
¥ Very low-power CMOS design
¥ Wait and stop low-power standby modes
¥ Fully-static logic, operation frequency down to 0 Hz (dc)
¥ Optimized cycle-by-cycle power management circuitry (instruction-dependent,
peripheral-dependent, and mode-dependent)
MOTOROLA
DSP56309UM/D
DSP56309 Overview
DSP56309 Core Description
1-7
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