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On-Chip Emulation Module
JTAG PORT/onCE MODULE INTERACTION
Table 10-12 TMS Sequencing for DEBUG_REQUEST (Continued)
Step
TMS
k
0
..................................................................
k
0
l
1
m
1
n
0
Run-Test/Idle
................................................
n
0
Run-Test/Idle
In Òstep nÓ the external command controller verifies that the OS[1:0] bits have the value
11, indicating that the chip has entered debug mode. If the chip has not yet entered
debug mode, the external command controller goes to Òstep bÓ, Òstep cÓ etc. until debug
mode is acknowledged.
Table 10-13 TMS Sequencing for ENABLE_ONCE
Step
TMS
a
1
Test-Logic-Reset
b
0
c
1
Select-DR-Scan
d
1
e
0
f
0
g
0
h
0
i
0
j
1
k
1
10-30
JTAG Port
OnCE Module
Shift-IR
Shift-IR
Exit1-IR
Update-IR
JTAG Port
OnCE Module
Run-Test/Idle
Select-IR-Scan
Capture-IR
Shift-IR
Shift-IR
Shift-IR
Shift-IR
Exit1-IR
Update-IR
DSP56309UM/D
Idle
The four bits of the JTAG
DEBUG_REQUEST (0111) are
shifted in while status is
Idle
Idle
Idle
Idle
This step is repeated, enabling an
external command controller to
Idle
Idle
Idle
Idle
Idle
Idle
The core status bits are captured.
Idle
The four bits of the JTAG
ENABLE_ONCE instruction
Idle
(0110) are shifted into the JTAG
instruction register while status is
Idle
Idle
Idle
Idle
The OnCE module is enabled.
Note
shifted out.
poll the status.
Note
Ñ
Ñ
Ñ
Ñ
shifted out.
Ñ
MOTOROLA
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