Table of Contents
Advertisement
Note:
Either a hardware RESET signal or a software RESET instruction clears all
PRR bits.
Table 7-5 shows the port signal configurations.
Table 7-5 Port Control Register and Port Direction Register Bits
7.6.3
Port Data Register (PDR)
The read/write, 24-bit PDR is used to read or write data to and from the ESSI GPIO
signals. The PD[5:0] bits are used to read or write data from and to the corresponding
port signals if they are configured as GPIO signals. If a port signal [i] is configured as a
GPIO input, then the corresponding PD[i] bit reflects the value present on this signal. If a
port signal [i] is configured as a GPIO output, then the value written into the
corresponding PD[i] bit is reflected on the this signal. Figure 7-20 shows the PDR bits.
7
6
PD5
STDn
15
14
23
22
Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility
Figure 7-20 Port Data Register (PDR) (PDRC X:$FFFFBD)
MOTOROLA
PC[i]
PDC[i]
1
X
0
0
0
1
Note:
X: The signal setting is irrelevant to port
signal [i] function.
5
4
3
2
PD4
PD3
PD2
SRDn
SCKn SCKn2 SCKn1 SCKn0
13
12
11
10
21
20
19
18
(PDRD X:$FFFFAD)
DSP56309UM/D
Enhanced Synchronous Serial Interface (ESSI)
GPIO Signals and Registers
Port Signal[i] Function
ESSI
GPIO input
GPIO output
1
0
PD1
PD0
PDRD: ESSI0, PDRD: ESSI1
9
8
17
16
AA0690
7-45
Advertisement
Chapters
Table of Contents
