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Host Interface (HI08)
HI08-External Host ProgrammerÕs Model
IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused addresses
(provided they have been pre-programmed in the DSP). HV is set to $32 (vector location
$0064) by a hardware RESET signal, software RESET instruction, individual reset, or a
STOP instruction.
6.6.2.2
CVR Host Command Bit (HC) Bit 7
The host processor uses the HC bit to handshake the execution of host command
interrupts. Normally, the host processor sets HC to request a host command interrupt
from the DSP56309. When the DSP56309 acknowledges the host command interrupt, the
HI08 hardware clears the HC bit. The host processor can read the state of HC to
determine when the host command has been accepted. After setting HC, the host must
not write to the CVR again until the HI08 hardware clears HC. Setting the HC bit causes
host command pending (HCP) to be set in the HSR. The host can write to the HC and HV
bits in the same write cycle.
6.6.3
Interface Status Register (ISR)
The interface status register (ISR) is an 8-bit, read-only status register used by the host
processor to interrogate the status and flags of the HI08. The host processor can write to
this address without affecting the internal state of the HI08. The DSP core cannot access
the ISR. The ISR bits are described in the following paragraphs. This register is
illustrated in Figure 6-14.
6.6.3.1
ISR Receive Data Register Full (RXDF) Bit 0
The RXDF bit indicates that the receive byte registers (RXH:RXM:RXL) contain data
from the DSP56309 and can be read by the host processor. RXDF is set when the HTX is
transferred to the receive byte registers. RXDF is cleared when the receive data (RXL or
RXH according to HLEND bit) register is read by the host processor. RXDF can be
cleared by the host processor using the initialize function. RXDF can assert the external
HREQ signal if the RREQ bit is set. Regardless of whether the RXDF interrupt is enabled,
RXDF indicates whether the RX registers are full and data can be latched out so that the
host processor can use polling techniques.
6-26
7
6
5
HREQ
HF3
ÑReserved bit. Read as 0. Should be written with 0, for future compatibility.
Figure 6-14 Interface Status Register
DSP56309UM/D
4
3
2
1
HF2
TRDY
TXDE
0
RXDF
AA0670
MOTOROLA
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