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Host Interface (HI08)
HI08-External Host ProgrammerÕs Model
6.6.7
Host Side Registers After Reset
Table 6-12 shows the result of the four kinds of reset on bits in each of the HI08 registers
seen by the host processor. The hardware reset is caused by asserting the RESET signal.
The software reset is caused by executing the RESET instruction. The individual reset is
caused by clearing the HEN bit in the HPCR. The stop reset is caused by executing the
STOP instruction.
Register
Register
Name
ICR
All Bits
CVR
HV[0:6]
ISR
HREQ
HF3 -HF2
TRDY
TXDE
RXDF
IVR
IV[0:7]
RX
RXH: RXM:RXL
TX
TXH: TXM:TXL
6.6.8
General-Purpose I/O
When configured as GPIO, the HI08 is viewed by the DSP56309 as memory-mapped
registers, as documented in Section 6.5ÑHI08 DSP Side ProgrammerÕs Model on
page 6-8. Those memory-mapped registers control up to 16 I/O signals. Software RESET
instructions and hardware RESET signals clear all DSP side control registers and
configure the HI08 as GPIO with all 16 signals disconnected. External circuitry
6-30
Table 6-12 Host Side Registers After Reset
Data
HW
Reset
0
HC
0
$32
0
0
1
1
0
$0F
empty
empty
DSP56309UM/D
Reset Type
SW
IR
Reset
Reset
0
Ñ
0
0
$32
Ñ
0
1 if TREQ is set;
0 otherwise
0
Ñ
1
1
1
1
0
0
$0F
Ñ
empty
empty
empty
empty
ST
Reset
Ñ
0
Ñ
1 if TREQ is set;
0 otherwise
Ñ
1
1
0
Ñ
empty
empty
MOTOROLA
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