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Serial Communication Interface (SCI)
GPIO Signals and Registers
7
6
5
13
15
14
21
23
22
Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility
Note:
A hardware RESET signal or a software RESET instruction clears all PRR bits.
Table 8-4 shows the port signal configurations.
Table 8-4 Port Control Register and Port Direction Register Bits
8.5.3
Port E Data Register (PDRE)
The read/write, 24-bit PDRE is used to read or write data to or from SCI GPIO signals.
Bits PD[2:0] are used to read or write data from or to the corresponding port signals if
they are configured as GPIO. If a port signal[i] is configured as a GPIO input, then the
corresponding PD[i] bit reflects the value of this signal. If a port signal[i] is configured as
a GPIO output, then the value of the corresponding PD[i] bit is reflected on this signal.
Bits of the Port E data register appear in Figure 8-10.
8-28
4
3
2
1
PDC2
PDC1
PDC0
12
11
10
9
20
19
18
17
Figure 8-9 Port E Direction Register (PRRE)
PC[i]
PDC[i]
1
1 or 0
0
0
0
1
DSP56309UM/D
0
Direction Control Bits: 1 = Output
8
16
Port Signal[i] Function
SCI
GPIO input
GPIO output
0 = Input
AA0696
MOTOROLA
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