Table of Contents
Advertisement
Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
7.4.1.7
CRA Word-length Control (WL[2:0]) Bits 21Ð19
The WL[2:0] bits are used to select the length of the data words being transferred via the
ESSI. Word lengths of 8-, 12-, 16-, 24-, or 32- bits can be selected, as in Table 7-2. The
ESSI data path programming model in Figure 7-16 on page 7-31 and Figure 7-17 on
page 7-32 has additional information about selecting different length data words. The
ESSI data registers are 24 bits long. The ESSI transmits 32-bit words either by duplicating
the last bit eight times when WL[2:0] = 100, or by duplicating the first bit eight times
when WL[2:0] = 101. The WL[2:0] bits are cleared by a hardware RESET signal or by a
software RESET instruction.
WL2
0
0
0
0
1
1
1
1
7.4.1.8
CRA Select SC1 (SSC1) Bit 22
The SSC1 bit controls the functionality of the SC1 signal. This bit is only valid when the
ESSI is configured in synchronous mode (i.e., if the CRB synchronous/asynchronous bit
(SYN) is set), and transmitter 2 is disabled (i.e., if transmit enable (TE2) = 0). If SSC1 is set
and SC1 is configured as an output (SCD1 = 1), then the SC1 signal acts as the driver
enabled signal of transmitter 0. This enables an external buffer for the transmitter 0
output.
If SSC1 is cleared, SC1 acts as the serial I/O flag.
7.4.1.9
CRA Reserved Bit 23
This bit is reserved. It is read as 0 and should be written with 0.
7-14
Table 7-2 ESSI Word Length Selection
WL1
WL0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
DSP56309UM/D
Number of Bits/Word
8
12
16
24
32
(valid data in the first 24 bits)
32
(valid data in the last 24 bits)
Reserved
Reserved
MOTOROLA
Advertisement
Chapters
Table of Contents
