Table 1.2
Pin Functions (cont)
No. Pin Name
I/O
202
/
O
203
/
I
204 MD6/
I
205
I
206 TXD
O
207 VDDQ
Power IO VDD
208 VSSQ
Power IO GND
209 VDD
Power Internal VDD
210 VSS
Power Internal GND
211 MD2/RXD2 I
212 RXD
I
213 TCLK
I/O
214 MD8/
I/O
215 SCK
I/O
216 MD1/TXD2 I/O
217 MD0/SCK2 I/O
218 MD7/
I/O
219 AUDSYNC
220 AUDCK
221 VDDQ
Power IO VDD
222 VSSQ
Power IO GND
223 AUDATA0
224 AUDATA1
Function
Reset
Bus
acknowledge/
bus request
Bus
request/bus
acknowledge
Mode/
MD6
(PCMCIA)
Bus ready
SCI data
output
Mode/SCIF
MD2
data input
SCI data input
RTC/TMU
clock
Mode/SCIF
MD8
data control
(RTS)
SCIF clock
Mode/SCIF
MD1
data output
Mode/SCIF
MD0
clock
Mode/SCIF
MD7
data control
(CTS)
AUD sync
AUD clock
AUD data
AUD data
Memory Interface
SRAM
DRAM
RXD2
RXD2
TXD2
TXD2
SCK2
SCK2
Rev. 3.0, 04/02, page 21 of 1064
SDRAM
PCMCIA MPX
RXD2
RXD2
TXD2
TXD2
SCK2
SCK2
RXD2
TXD2
SCK2