Figure 14.15
Dual Address Mode/Burst Mode External Bus
Figure 14.16
Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection)
External Bus..................................................................................................... 509
Figure 14.17
Dual Address Mode/Cycle Steal Mode External Bus
(Level Detection) ............................................................................................. 510
Figure 14.18
Single Address Mode/Cycle Steal Mode External Bus
(Level Detection) ............................................................................................. 511
Figure 14.19
Single Address Mode/Cycle Steal Mode External Bus
(Edge Detection) .............................................................................................. 512
Figure 14.20
Single Address Mode/Burst Mode External Bus
(Level Detection) ............................................................................................. 513
Figure 14.21
Single Address Mode/Burst Mode External Bus
(Edge Detection) .............................................................................................. 514
(Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM:
Row Hit Write) ................................................................................................ 515
latency=3, TPC=3)........................................................................................... 526
TRWL=2, TPC=1) ........................................................................................... 527
Block Transfer/Channel 0 On-Demand Data Transfer .................................... 529
Block Transfer/Channel 0 On-Demand Data Transfer .................................... 529
Transfer) .......................................................................................................... 533
External Bus/
On-Chip SCI
External Bus/
External Bus/
External Bus/
External Bus/
Rev. 3.0, 04/02, page xxv of xxxviii