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Table 9.4
State of Registers in Standby Mode
Module
Interrupt controller
User break controller
Bus state controller
On-chip oscillation circuits
Timer unit
Realtime clock
Direct memory access controller
Serial communication interface
Notes: DMA transfer should be terminated before making a transition to standby mode. Transfer
results are not guaranteed if standby mode is entered during transfer.
* Not initialized when the realtime clock (RTC) is in use (see section 12, Timer Unit (TMU)).
The procedure for a transition to standby mode is shown below.
1. Clear the TME bit in the WDT timer control register (WTCSR) to 0, and stop the WDT.
Set the initial value for the up-count in the WDT timer counter (WTCNT), and set the clock to
be used for the up-count in bits CKS2–CKS0 in the WTCSR register.
2. Set the STBY bit in the STBCR register to 1, then execute a SLEEP instruction.
3. When standby mode is entered and the chip's internal clock stops, a low-level signal is output
at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
9.6.2
Exit from Standby Mode
Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a
reset via the
and
Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI,
IRL *
1
, RTC, or GPIO *
clocks are supplied to the entire chip, standby mode is exited, and the STATUS1 and STATUS0
pins both go low. Interrupt exception handling is then executed, and the code corresponding to the
interrupt source is set in the INTEVT register. In standby mode, interrupts are accepted even if the
BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack
before executing the SLEEP instruction.
The phase of the CKIO pin clock output may be unstable immediately after an interrupt is
detected, until standby mode is exited.
Rev. 3.0, 04/02, page 226 of 1064
Initialized Registers
—
—
—
—
TSTR register*
—
—
See Appendix A, Address List See Appendix A, Address List
pins.
2
interrupt is detected, the WDT starts counting. After the count overflows,
Registers That Retain
Their Contents
All registers
All registers
All registers
All registers
All registers except TSTR
All registers
All registers
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