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IPRD
Bit:
15
Initial value:
1
R/W:
R/W
Bit:
7
Initial value:
0
R/W:
R/W
Table 19.5 shows the relationship between the interrupt request sources and the IPRA–IPRD
register bits.
Table 19.5 Interrupt Request Sources and IPRA–IPRD Registers
Register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Notes: *1 REF is the memory refresh unit in the bus state controller (BSC). See section 13, Bus
State Controller (BSC), for details.
*2 Reserved bits: These bits are always read as 0 and should always be written with 0.
As shown in table 19.5, four on-chip peripheral modules are assigned to each register. Interrupt
priority levels are established by setting a value from H'F (1111) to H'0 (0000) in each of the four-
bit groups: 15–12, 11–8, 7–4, and 3–0. Setting H'F designates priority level 15 (the highest level),
and setting H'0 designates priority level 0 (requests are masked).
19.3.2
Interrupt Control Register (ICR)
The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for
external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register
is initialized by a power-on reset or manual reset. It is not initialized in standby mode.
Rev. 3.0, 04/02, page 740 of 1064
14
13
1
0
R/W
R/W
6
5
1
1
R/W
R/W
15–12
TMU0
WDT
GPIO
IRL0
12
11
1
1
R/W
R/W
R/W
4
3
1
0
R/W
R/W
R/W
Bits
11–8
7–4
TMU1
TMU2
1
REF*
SCI1
DMAC
SCIF
IRL1
IRL2
10
9
0
1
R/W
R/W
2
1
1
0
R/W
R/W
3–0
RTC
Reserved*
H-UDI
IRL3
8
0
0
0
2
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