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System/CPU Overview
CPU
Q
Register
8M Register
SR Register
C:-------.
('-_ - -----.1
S
(SM)
+
(SR)
Address
Address
+
3
MEMORY
Stack
Figure 2-10.
CPU TOS Registers
as an example, the hardware will define address S as being
equal
to the SM Register value plus three.
The value three is obtained
from the SR Register which, as previously discussed, retains
the
number of
TOS elements that are in the TOS registers.
(S
=
SM
+
SRi
RA
=
S, RB
=
S - 1, etc.)
The address
val ue
S obtained
by
adding
the SR Register contents to the SM Register contents is a
completely valid address.
In fact, when the CPU must be
cleared
for some other operation (e.g., a new procedure or an interrupt),
the register contents are physically transferred to
the
numeri-
cally
corresponding memory locations.
In this example, SM would
move up by three and the SR Register contents would become zero.
Figure 2-11 illustrates the actions of the Q Register in
marking
the
starting
location
for
each procedure's data.
Figure 2-11
shows that the currently executing code segment was working
with
data
in the
temporary
storage
area immediately
following the
First Q area.
At that time, the Q Register was pointing at First
Q, S was defining TOS, and the Z Register was pointing to the end
of the data segment.
(If the executing code segment never
called
another procedure,
the stack would never get more
complica ted.)
As illustrated however, the code called a procedure at
some
point
by means of a
Procedure Call (peAL) instruction that
caused ad-
ditions to
the stack as indicated
by Procedure A.
New data was
incurred as the procedure began and S pointed to the top of
that
data as
it was generated.
Then, Procedure A
called Procedure B
2-24
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