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MCU/Main Memory Overview
Bits 6-15
Address.
The 10 bit address
(1024)
locations is the
starting address
for a Write Cbpy of
the I/O Logging
Array to the Error Logging Array, a Load Block of
the
I/O Logging Array, or the address for a Load Single of
the I/O Logging Array.
6-47. RIO Command.
Figure 6-13 shows the
word
format
for
the
RIO instr uction.
RIO
I
I
I
I
I
I
0
1
2 3 4 5
6
'I
as
~
10
11
12
13
14
15
I
ERROR~
MSB
LSB
R/WOK
\..
J
=0
Y
10 BIT ADDRESS
READ SCAN
DISWEC
UU512K
Figure 6-13.
RIO Word Format
Bit 0
Bit 1
This bit is
set if there was an error
logged in
the
I/O
Logging Array during a Read Scan
and the address
of that error is specified by bits 6 through 15.
R/W OK.
This bit contains the same information as R/W
OK on a TIO instruction.
Bit 3
Read Scan.
This bit is set when a
process
and remains set until the
mination of a scan.
Read
Scan
is
in
completion or ter-
Bit 4
Bit 5
Bit 6-15
DISWEC.
This bit is set if the
Disable Error Correc-
tion flip-flop is set.
L/NU 512K.
If bit 5
=
1, the upper 512K Error Logging
Array has been selected and,
if bit 5
=
0,
the lower
512K Error Logging Array has been selected.
Address.
This is the I/O
Logging Array address
of a
logged error during a Read Scan.
6-48. SMA PCA SERVICING.
Although the SMA PCA can be repaired to
the component level, repair procedures should be
attempted
only
by
persons
specificaly trained for such tasks.
The replaceable
components are identified in figure 6-5. (For additional informa-
tion, refer to the HP 3000 Series III Computer System Engineering
Diagrams Set, part no. 30000-90173.) Each SMA PCA in
the
memory
6-27
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