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INTERRUPT SYSTEM
I~
This section
contains principles of operation and
servicing in-
formation for the computer's interrupt system.
8-1. INTRODUCTION
The computer's interrupt
system provides up to 125 external lev-
els.
When interrupts occur,
the microprogrammed interrupt hand-
ler identifies
each interrupt and grants control to
the highest
priority interrupt.
Current operational
status is
retained by
the microprogram which then sets up the interrupt
processing en-
vironment and transfers control to the interrupt routine.
Interrupt routines operate on a common stack called the Interrupt
Control Stack (ICS) which is known to both software and hardware.
This feature permits nesting of interrupt routines in the case of
multiple interrupts,
thus allowing
higher
priority
devices to
interrupt lower priority devices.
The interrupt
system also
provides for
17
internal interrupts
(user errors, system violations, hardware faults, and power fail/
restart) plus
seven traps for arithmetic errors and illegal
use
of instructions.
8-2. INTERRUPT SYSTEM OVERVIEW
The interrupt system's interrupt routines are called
and
exited
in
a· manner
resembling
the way that procedures are called and
exited.
An interrupt is therefore an implicit
PCAL
instruction
(vs. an explicit PCAL instr uction) •
(Refer to section IV.) _Also,
code and data domains are kept separate.
The primary differences
are that the calling operations
are
performed
by
a
micropro-
grammed
Interrupt
Handler rather than the PCAL instruction and,
in some cases, the IXIT (Interrupt Exit) instruction is used
for
exiting
the
interrupt code instead of EXIT.
Internal interrupt
procedures are contained in code
segment
number
1.
Interrupt
procedures
for I/O devices may be in any code segment other than
segment number 1.
Table 8-1 lists the
internal
interrupts
and
traps
with
their
corresponding
entry
numbers
in the Segment
Transfer Table (STT) of the internal interrupt code segment.
The
'parameter is a value that is derived by the Interrupt Handler and
which passes relevant information
about
the
interrupt
to
the
interrupt
routine.
The Device Reference Table (DRT) contains a
label for each entry, pointing to
the
interrupt
procedure
for
each
device.
Bit 8 of the CPXl Register indicates an external
interrupt.
The parameter value for an external interrupt is
the
device numbe r.
8-1
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