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I/O System
7-60.
End.
The execute sequence for the
End
order begins
by
duplicating the
operations of a Sense order,
obtaining the con-
troller's status word and storing it in the IOAW location in
the
I/O program.
Additionally,
if IOCW bit 4 {s true,
a P SET INT
signal is also issued to the controller. (Refer to Interrupt order
description.)
Then the channel proceeds to store the contents of
its I/O Program Cbunter into the device's DRT location.
As pre-
viously discussed,
this is to
maintain
compatibility with
I/O
programs
run via a
Multiplexer Channel.
The selector
Channel
enables its DEVNO DB Register,
enables the
I/O
Program Counter
for use as data, and sends a Write Request and a TO=O to the Port
Controller.
When the port returns LSEL,
the shifted device num-
ber is gated
out as the
DRT address and,
when the port returns
HSEL, the I/O Program Counter content is gated out to the bus
as
data.
This completes all operations for the
I/O program.
The
channel control logic resets to the inactive condition,
thus al-
lowing another
program for the same or
another device to be in-
itiated via that channel.
7-61 I/O SYSTEM SERVICING INFORMATION
The following
paragraphs contain servicing
lOP,
Mul tiplexer Channel, Por t Controller,
PCA's.
information for
the
and Selector Channel
7-62. lOP PCA Servicing
The lOP PCA is a nonrepair able ,PCA and must be replaced if
found
defective.
No repair procedures are required.
However, the lOP
PCA does contain a jumper and three switches
(figure 7-20)
that
must
be
properly
configured
as
discussed
in paragraphs 7-63
through 7-65.
7-63.
ENABLE/DISABLE.
or disable the lOP PCA.
lOP PCA.
Jumper
WI
(figure 7-20)
is used to enable
Installation of this jumper disables the
7-64.
MEMORY SIZE.
Switch S3
(figure
7-20)
is
a
6-position
switch used to select memory word .size.
The switch positions and
corresponding memory word sizes are shown in figure 7-20.
7-65.
MEMORY INTERLEAVING.
Two switches, Sl and S2
(figure
7-
20),
are used
for memory interleaving.
At present,
Sl and S2
must be configured for non-interleaving in accordance with
table
2-8.
7-66. Selector Channel Maintenance Board PCA
The Selector Channel Maintenance Board PeA was designed to aid in
servicing the
Selector Channel and
MUltiplexer Channel.
Under
software control, this PCA can exercise all Selector Channel data
paths and control circuitry.
All I/O program orders can be exe-
cuted and
device dependent
sequences such as
conditional jump,
7-46
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