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System/CPU Overview
The lOP provides the I/O control link for the computer system and
resolves priority
conflicts
for
I/O
interrupts
and
multiple
Multiplexer
Channel
access
to
the
CTL Bus.
The lOP performs
different
functions for each
of the three
IT/O
transfer modes.
(Refer to
Section
VII.)
During direct
F/O transfer
mode and
depending on
received direct
rio
instructions
(RIO,
vlIO,
TIO,
CIO,
SIN,
and SMSK),
the
lOP
transfers
either data,
device
status,
or control information between the CPU and a Device Con-
troller.
During programmed
I/O transfer mode via a Multiplexer
Channel,
the lOP transfers
rio
program words between memory
and
the
Multiplexer Channel, and transfers data between memory and a
Multiplexer-Channel-selected
Device
Controller.
During
pro-
grammed
rio
transfer mode via a Selector Channel,
the lOP only
transfers
initialization
information
to
a
Device
Controller
associated with the Selector Channel; it does not become involved
in any part of the
rio
program execution.
During all
rio
trans-
fer modes,
the lOP
interrup.ts the
CPU on behalf of
the Device
Controllers.
The lOP shares the MCU with the CPU.
Physically,
the Central Processor Module consists of
nine PCA's
contained
in
slots
A2 through AIO of card Cage No.1 of all HP
3000 Series III Computer
System
models.
Card
Cage No.1 is
a
dedicated card
cage module and the
nine PCA's must be installed
exactly as shown in tables 1-1 through 1-3.
2-11.
MAIN MEMORY.
Main Memory is a high-speed,
semiconductor,
randan
access memory
that
provides high-speed
storage for the
computer system.
Main Memory operates
as an
error
correcting
memory with
single-bit fault
correction and some doUble-bit de-
tection. (Main Memory can operate as a non-error correcting
mem-
ory
with a
par ity
bi t,
but
th
is is not
the normal opera ting
mode.) Main Memory
can vary in size from 128K (K=1024) words
to
l024K words and, due to its modular design, it can easily be
ex-
panded from one size to another.
A maximum word
capaci ty system
(consists of 16
64K-word
memory
banks
(Bank 0 through Bank 15) divided into two 512K-word memory
modules.
Each 512K-word memory module contains its own MCU which
controls word transfers
between the module and the
other system
modules
connected to
the CTL Bus.
The word length transmitted
over the CTL
Bus is 17 bits; 16 bits of data
(one
word or
two
bytes)
and one
parity
bit.
(Within
the memory modules,
word
length is expanded to 22 bits;
16 bits of data and six bits
for
automatic fault detection and correction.)
A detailed discussion
of
~~in
Memory is contained in Section VI.
Physically, Main Memory consists of three basic PCA':s
configured
as shown in table 2-2.
It should be noted that each Semiconduct-
or Memory Array (SMA) PCA contains 128K words of memory, that one
Memory Control and Logging (MCL) PCA can support up to
four
SMA
PCA's
(512K), and that one Fault Logging Interface (FLI) PCA can
support the computer system's maximum memory
capacity
of
eight
S~~
PCA's
(1024K).
The Main Memory PCA's are arranged in Card
Cages No.2 and No.3 as shown in tables 1-1 through 1- 3.
Conven-
tionally, card cage slots 2A6 through 2A9 (HP 32421A
Series III)
2-4
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