Table 6-26: 320X240 Sharp 'Direct' Hr-Tft Panel Horizontal Timing; Table 6-27: 320X240 Sharp 'Direct' Hr-Tft Panel Vertical Timing; Figure 6-33: 320X240 Sharp 'Direct' Hr-Tft Panel Vertical Timing - Epson S1D13706 Technical Manual

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Table 6-26: 320x240 Sharp 'Direct' HR-TFT Panel Horizontal Timing

FPLINE start position

Horizontal total period

FPLINE width

FPSHIFT period

Data setup to FPSHIFT rising edge

Data hold from FPSHIFT rising edge

Horizontal display start position

Horizontal display period

FPLINE rising edge to GPIO3 rising edge

GPIO3 pulse width

GPIO1(GPIO0) pulse width

GPIO1 rising edge (GPIO0 falling edge) to FPLINE rise edge

GPIO2 toggle edge to FPLINE rise edge

= pixel clock period

= (REG[22h] bits 7-0) + 1

= ((REG[12h] bits 6-0) + 1) x 8

= (REG[20h] bits 6-0) + 1

= ((REG[16h] bits 7-0) + 5) - ((REG[22h] bits 7-0) + 1)

= ((REG[14h] bits 6-0) + 1) x 8

Vertical total period

Vertical display start position

Vertical display period

Vertical sync pulse width

Hardware Functional Specification

Issue Date: 01/11/13

X31B-A-001-08

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