Epson S1D13706 Technical Manual page 439

Embedded memory lcd controller

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Epson Research and Development

Vancouver Design Center

Interfacing to the PC Card Bus

Issue Date: 01/02/23

During a read cycle, -OE (output enable) is driven low. A write cycle is specified by driving

-OE high and driving the write enable signal (-WE) low. The cycle can be lengthened by

driving -WAIT low for the time needed to complete the cycle.

Figure 2-1: illustrates a typical memory access read cycle on the PC Card bus.

Transfer Start

Figure 2-1: PC Card Read Cycle

Figure 2-2: illustrates a typical memory access write cycle on the PC Card bus.

Transfer Start

Figure 2-2: PC Card Write Cycle

ADDRESS VALID

Transfer Complete

ADDRESS VALID

Transfer Complete

X31B-G-005-02

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